The present invention deals with analog-to-digital (A/D) converters. More specifically, the present invention is a system for calibrating A/D converters.
Charge balanced A/D converters are generally known. An example of a charge balanced A/D converter is a dual slope A/D converter which includes an integrator, a reference current source which applies a reference current I.sub.REF to the integrator, and a variable current source that provides a variable current I.sub.X which is representative of an unknown variable. In a dual slope A/D conversion, the variable current, I.sub.X, is integrated for a time period, t.sub.X. The quantity of charge, Q, accumulated in the integrator is equal to I.sub.X times t.sub.X. A known reference current I.sub.REF, having a polarity opposite that of I.sub.X, is then applied to the integrator to remove charge from the integrator (i.e., discharge the integrator). The reference current I.sub.REF is applied for a time period t.sub.R until the charge on the integrator reaches the initial charge level on the integrator prior to integration of the variable current I.sub.X. The charge removed from the integrator is equal to I.sub.REF times t.sub.R.
The variable current I.sub.X (and hence the unknown variable) is determined as follows: EQU I.sub.X .multidot.t.sub.X =I.sub.REF .multidot.t.sub.R Eq. 1
Therefore, ##EQU1##
Since I.sub.REF, t.sub.R and t.sub.X are all known, I.sub.X can be calculated.
A problem with conventional dual slope A/D converters is that they typically have a very limited dynamic range which is determined by the minimum and maximum power supply voltages of the circuit (e.g., the rail voltages, which are typically zero to five volts). For instance, the integrator cannot change above or below the rail voltages. This places limitations on either the charging currents or the integration time or both. This, in turn, limits the range of the converter.
In order to overcome this problem, A/D converters have been operated by adding a comparator to the circuit and determining when the output of the integrator is approaching the rail voltage. As the output of the integrator approaches the rail voltage, the reference current is applied to the integrator along with the variable current to remove charge from the integrator so that the integration can be done over a longer period of time to effectively increase the dynamic range of the integrator. Such operation requires the reference current I.sub.REF to have a greater magnitude than the magnitude of variable current I.sub.X. This allows application of I.sub.REF to remove charge from the integrator quickly enough so that the integrator does not approach the rail voltage, even while I.sub.X is still being integrated.
However, setting the magnitude of I.sub.REF to be significantly larger than I.sub.X decreases the resolution of the A/D converter. In order to add resolution to the A/D converter, a second reference current source I.sub.REF2 has been added to the dual slope A/D converter. The second reference current I.sub.REF2 has a smaller magnitude than that of the first reference current I.sub.REF. Thus, after the variable current I.sub.X has been integrated, and the first reference current I.sub.REF discharges the integrator for a desired time period t.sub.R, then the second reference current I.sub.REF2 discharges any residual charge on the integrator. Since the magnitude of the second reference current is significantly smaller than the magnitude of the first reference current, the resolution of the A/D converter is greatly increased.
Adding a second reference current source, however, has introduced additional problems. For example, the accuracy of the A/D converter output is highly dependent upon the precise ratio between the two reference currents I.sub.REF and I.sub.REF2. If the ratios are different than expected, differential errors or non-linearities can occur in the A/D converter output which are very difficult to correct.
Prior attempts to alleviate this problem involved custom layout of current sources on silicon, which are error prone and require significant amounts of development time. Special integrated circuit manufacturing steps add cost, undesired complexity and also limit the portability of the design between silicon manufacturing facilities, so that a precise ratio between the current sources is very difficult to obtain.